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ts3002 page 1 ? 2014 silicon laboratories, inc. all rights reserved. features ? ultra low supply current: 1a at 25khz ? supply voltage operation: 0.9v to 1.8v ? programmable frequency range: o 5.2khz fout 90khz (boost = gnd) o 5.2khz fout 290khz (boost = vdd) ? fout period drift: 0.044%/ c ? pwmout duty cycle range: 12% to 90% ? single resistor and capacitor set output frequency ? output driver resistance: 160 ? applications portable and battery-powered equipment low-parts-count na nopower oscillator compact nanopower replacement for crystal and ceramic oscillators nanopower pulse-width modulation control nanopower pulse-position modulation control nanopower clock generation nanopower sequential timing description the ts3002 is the industry?s first and only single- supply cmos oscillator fully specified to operate at 1v while consuming a 1a supply current at an output frequency of 25khz. th is oscillator is compact, easy-to-use, and versatile. optimized for ultra-long life, battery-powered applications, the ts3002 is the first oscillator in the ?nanowatt analog?? high- performance analog integrated circuits portfolio. the ts3002 can operate from singl e-supply voltages from 0.9v to 1.8v. requiring only a resistor and a capacitor to set the output frequency, the ts3002 represents a 66% reduction in pcb area and a factor-of-10 reduction in power consumption ov er other cmos-based integrated circuit oscillators. when compared against industry-standard 555-timer-based products, the ts3002 offers up to 93% reduction in pcb area and four orders of magnitude lower power consumption. the ts3002 is fully specified over the -40c to +85c temperature range and is ava ilable in a low-profile, 8- pin 2x2mm tdfn package with an exposed back- side paddle. a 1v/1a easy-to-use silicon oscillator/timer typical application circuit table 1: fout vs r set , c set = 7.9pf r set (m? ) fout (khz) 1 106 2.49 43 4.32 25 6.81 16 9.76 11 table 2: fout vs c set , r set = 4.32m ? c set (pf) fout (khz) 5 39 7.9 25 10 19 15 13 20 10
ts3002 page 2 ts3002 rev. 1.0 absolute maximum ratings v dd to gnd.................................................................... -0.3v to +2v v cntrl to gnd ............................................................... -0.3v to +2v rset to gnd ................................................................ -0.3v to +2v cset to gnd ................................................................ -0.3v to +2v fout, pwmout to gnd ............................................. -0.3v to +2v short circuit duration fout , pwmout to gnd or v dd .................................................................................. continuous continuous power dissipation (t a = +70c) 8-pin tdfn (derate at 23.8mw/c above +70c) ....... 1951mw operating temperature range ................................. -40c to +85c storage temperature range .................................. -65c to +150c lead temperature (soldering, 10s) ...................................... +300c electrical and thermal stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the op erational sections of the specifications is not implied. ex posure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. package/ordering information order number part marking carrier quantity ts3002itd822 aah tape & reel ----- TS3002ITD822T tape & reel 3000 lead-free program: silicon labs supplies only lead-free packaging. consult silicon labs for produ cts specified with wider oper ating temperature ranges.
ts3002 ts3002 rev. 1.0 page 3 electrical characteristics v dd = 1v, v cntrl = v dd , v boost = 0v, r set = 4.32m? , c set = 7.9pf, r load(fout) = open circuit, c load(fout) = 0pf, c load(pwm) = 0pf unless otherwise noted. values are at t a = 25c unless otherwise noted. see note 1. parameter symbol conditions min typ max units supply voltage v dd 0.9 1 1.8 v supply current i dd 1 1.5 a -40c t a 85c 2.8 v cntrl = 0.15 x v dd 2.1 3.7 -40c t a 85c 5.4 v boost = v dd 2.16 3.2 -40c t a 85c 4.8 v boost = v dd, v cntrl = 0.15 x v dd 3.6 5.3 -40c t a 85c 7.3 fout period t fout 37 40.6 44 s -40c t a 85c 34.7 45.6 v boost = v dd 36 39.5 43 -40c t a 85c 33 48 fout period line regulation ? t fout /v 1v v dd 1.8v 1.3 %/v v boost = v dd -1.6 fout period temperature coefficient ? t fout /? t 0.044 %/c v boost = v dd 0.086 pwmout duty cycle dc(pwmout) v cntrl = 0.03 x v dd 4.5 8.9 13 % v cntrl = 0.15 x v dd 44 49.3 54 v cntrl = 0.27 x v dd 83 90.5 97 v cntrl = 0.03 x v dd v boost = v dd 4.5 8.5 12.5 v cntrl = 0.15 x v dd 47 50.4 54 v cntrl = 0.27 x v dd 86 91.2 96 fout, pwmout rise time t rise see note 2, c l = 15pf 8.6 ns fout, pwmout fall time t fall see note 2, c l = 15pf 7.9 ns fout jitter see note 3 0.08 % rset pin voltage v(rset) 0.3 v cntrl output current i cntrl 25 45 na -40c t a 85c 80 pwmout enable v pwm_en (v dd - v cntrl ), 0.9v < v dd < 1.8v 375 mv pwmout disable v pwm_dis (v dd - v cntrl ), 0.9v < v dd < 1.8v 131 mv boost enable v ih (v dd ? v boost ), 0.9v < v dd < 1.8v 77 mv boost disable v il 0.9v < v dd < 1.8v 77 mv boost input current i boost 10 na high level output voltage, fout and pwmout v dd - v oh i oh = 1ma 160 mv low-level output voltage, fout and pwmout v ol i ol = 1ma 140 mv note 1: all devices are 100% production tested at t a = +25c and are guaranteed by characterization for t a = t min to t max , as specified. note 2: output rise and fall times are measured between the 10% and 90% of the v dd power-supply voltage levels. the specification is based on lab bench characterization and is not tested in production. note 3: timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. the specification is based o n lab bench characterization and is not tested in production.
ts3002 page 4 ts3002 rev. 1.0 typical performance characteristics v dd = 1v, v cntrl = v dd , v boost = 0v, r set = 4.32m ?, c set = 7.9pf, r load(fout) = open circuit, c load(fout) = 5pf, unless otherwise noted. values are at t a = 25c unless otherwise noted. period - s supply current - a 40 80 1.5 0.5 supply current vs fout period 0 120 2 2.5 1 160 200 period - s supply current - a 4.3 1.5 8.5 supply current vs fout period 5.7 7.1 2.9 c load - pf supply current - a 10 20 2.4 2 3 supply current vs c load(fout) 0 30 2.6 2.8 2.2 40 3.2 40 80 0 120 160 200 c load - pf supply current - a 10 20 1.2 0.8 1.8 supply current vs c load(fout) 0 30 1.4 1.6 1 40 2 boost = v dd boost = v dd boost = gnd boost = gnd temperature - oc supply current - a 1.08 0.8 supply current vs temperature 1.22 1.36 0.94 1.5 -15 10 -40 35 60 85 temperature - oc supply current - a 2.24 1.6 supply current vs temperature 2.56 2.88 1.92 3.2 -15 10 -40 35 60 85 boost = v dd boost = gnd
ts3002 ts3002 rev. 1.0 page 5 typical performance characteristics v dd = 1v, v cntrl = v dd , v boost = 0v, r set = 4.32m ?, c set = 7.9pf, r load(fout) = open circuit, c load(fout) = 5pf, unless otherwise noted. values are at t a = 25c unless otherwise noted. temperature - oc period - s -15 10 40.5 39.5 42 fout period vs temperature -40 35 41 41.5 40 60 85 42.5 43 temperature - oc period - s -15 10 39 38 fout period vs temperature -40 35 39.5 40 38.5 60 85 40.5 41 41.5 boost = v dd boost = gnd supply voltage - volt period - s 1.05 1.2 40.6 40.4 41.2 fout period vs supply voltage 0.9 1.35 40.8 41 1.5 1.65 1.8 supply voltage - volt period - s 1.05 1.2 39 38.8 39.6 fout period vs supply voltage 0.9 1.35 39.2 39.4 1.5 1.65 1.8 39.8 40 boost = v dd boost = gnd r set - m ? period - s 48 80 0 200 period vs r set 0 12 120 160 40 16 20 boost = v dd r set - m ? period - s 4 8 80 0 200 period vs r set 0 12 120 160 40 16 20 boost = gnd
ts3002 page 6 ts3002 rev. 1.0 typical performance characteristics v dd = 1v, v cntrl = v dd , v boost = 0v, r set = 4.32m ? , c set = 7.9pf, r load(fout) = open circuit, c load(fout) = 5pf, unless otherwise noted. values are at t a = 25c unless otherwise noted. c set - pf period - s 8 12 60 20 period vs c set 4 80 100 40 16 20 c set - pf period - s 8 12 60 20 period vs c set 4 80 100 40 16 20 0 0 boost = v dd boost = gnd percent of units - % supply current - a 0% supply current distribution 0.97 5% 10% 15% 20% 25% 30% 35% 0.99 1.01 1.03 supply voltage - volt start-up time - ms 1.2 1.24 1.1 1.66 start-up time vs supply voltage 0.9 1.38 1.52 1.5 1.8 1.8
ts3002 ts3002 rev. 1.0 page 7 fout transient response v dd = 1v, boost = v dd , c load = 47 p f 5s/div fout 200mv/div fout transient response v dd = 1.5v, boost = v dd , c load = 47 p f 5s/div fout 500mv/div fout and pwmout transient response v dd = 1v, v cntrl = 0.035 x v dd , boost = v dd , c load = 22 p f 5s/div fout 500mv/div pwmout 500mv/div
ts3002 page 8 ts3002 rev. 1.0 pin functions pin name function 1 fout fixed frequency output. a push-pull output stage with an output resistance of 160 ? , the fout pin swings from gnd to v dd . for lowest power operation, capacit ive loads should be minimized and resistive loads should be maximized. 2 boost boost input. a digital switch input, boost controls the propagation delay of the primary timing comparator in the ts3002?s master oscillator subcircuit. connecting the boost pin to gnd sets the maximum programmable oscillator frequency to ~90khz.connecting the boost pin to vdd reduces the comparator?s propagation delay and increases the maximum programmable master oscillato r?s frequency to 290khz. 3 pwmout pulse-width modulated output. a push-pull output stage with an output resistance of 160 ? , the pwmout pin is wired anti-phase with respect to fout and swings from gnd to v dd . for lowest power operation, capacitive loads should be minimized and resistive loads should be maximized. 4 cntrl pwmout enable and duty cycle control input. an analog input pin, the v cntrl pin voltage enables the ts3002?s pwm engine and controls the duty cycle at pwmout from 12% (v cntrl = 0.03 x v dd ) to 90% (v cntrl = 0.27 x v dd ). enabling the pwm engine increases the ts3002?s nominal operating supply current. to disable the ts3002?s pwm engine, cntrl shall be connected to v dd . 5 cset fout programming capacitor input. a 7.9pf capacitor connected from this pin to gnd in junction with a 4.32m ? resistor at the rset pin sets the ts3002?s internal oscillator?s output period to ~40s (25khz). the maximum capacitance value is 22pf. 6 gnd ground ? connect this pin to the system?s analog ground plane. 7 rset fout programming resistor input. a 4.32m ? resistor connected from this pin to gnd sets the ts 3002?s internal oscillator?s output period to 40 s (25khz). for optimal performance, the composition of the rset resistor shall be consistent with tolerances of 1% or lower. the rset pin voltage is 0.3v at a 1v supply. 8 vdd power supply voltage input. while the ts3002 is fully specified at 1v, the supply voltage range is 0.9v v dd 1.8v. it is always considered good engineering practice to bypass the v dd pin with a 0.1 f ceramic decoupling capacitor in close proximity to the ts3002. ep ----- exposed paddle is elec trically connected to gnd.
ts3002 ts3002 rev. 1.0 page 9 block diagram theory of operation the ts3002 is a user-pro grammable oscillator where the period of the square wave at its fout terminal is generated by an external resistor and capacitor pair. the output frequency is given by: fout (khz) = 1 t fout (s) 1e6 k ? r set m ? x c set (pf) where the scalar k is approximately 1.19. with an r set = 4.32m ? and a c set = 7.9pf, the output frequency is approximately 25khz with a 50% duty cycle. as design aids, tables 1 lists ts3002?s typical fout for various standard values for r set with c set = 7.9pf and table 2 lists typical fout for various standard values for c set with r set = 4.32m ? . the ts3002 also provides a separate pwm output table 1: fout vs r set , c set = 7.9pf r set (m? ) fout (khz) 1 106 2.49 43 4.32 25 6.81 16 9.76 11 table 2: fout vs c set , r set = 4.32m ? c set (pf) fout (khz) 5 39 7.9 25 10 19 15 13 20 10
ts3002 page 10 ts3002 rev. 1.0 signal at its pwmout termi nal that is anti-phase with respect to fout. in addition, applying a voltage at the cntrl both enables the ts3002?s internal pwm engine as well as adjusting the duty cycle from 12% to 90%. a dc control voltage equal to 0.03 x vdd applied to the cntrl pin enables the pwm engine to set the duty cycle to 12%. a dc control voltage equal to 0.27 x vdd increases the duty cycle to 90% and connecting cntrl to vdd disables the pwm engine altogether. configured for nominal operation (pwm engine off, boost pin to gnd), the supply current of the ts3002 is 1a; enabling the pwm engine increases the ts3002 operating supply current as shown in the electrical specification table. the boost pin controls the propagation delay of the ts3002?s internal comparators. when boost is connected to gnd, the ts3002?s maximum programmable operating frequency is ~90khz. connecting the boost pin to vdd reduces the propagation delay of the inte rnal oscillators, thereby extending the high end maximum operating frequency to 290khz. applications information minimizing power consumption to keep the ts3002?s power consumption low, resistive loads at the fout and pwmout terminals increase dc power consum ption and therefore should be as large as possible. capacitive loads at the fout and pwmout terminals increase the ts3002?s transient power consumption and, as well, should be as small as possible. one challenge to minimizing the ts3002?s transient power consumption is the probe capacitance of oscilloscopes and frequency counter instruments. most instruments exhibit an input capacitance of 15pf or more. unless buffered, the increase in transient load current can be as much as 400na. to minimize capacitive loading, the technique shown in figure 1 can be used. in this circuit, the principle of series-connected capacitors can be used to reduce the effective capacitive load at the ts3002?s fout and pwmout terminals. to determine the optimal value for c ext once the probe capacitance is known by simply solving for c ext using the following expression: c ext = 1 1 c load(eff) - 1 c probe for example, if the instrument?s input probe capacitance is 15pf and the desired effective load capacitance at either or both fout and pwmout terminals is to be 5pf, then the value of c ext should be 7.5pf. ts3002 start-up time as the ts3002 is powered up, its fout terminal (and pwmout terminal, if enabled) is active once the applied vdd is higher than 0.9 volt. once the applied vdd is higher than 0.9 volt, the master oscillator achieves steady -state operation within 1.2ms. current- and voltage-controlled oscillators the ts3002 can be configured into a current-controlled oscillato r as shown in figure 2. with a current source sour cing a current of 223na to 262na, fout can generate an output signal with a frequency range of 5.2khz to 90khz. in a similar manner, a voltage-controlled oscillator can be configured as shown in figure 3. in this case, a voltage source sourcing a voltage of 290mv to figure 1: using an external capacitor in series with probes reduces effective capacitive load. figure 2: configuring the ts3002 into a current-controlled oscillator.
ts3002 ts3002 rev. 1.0 page 11 341mv can generate an fout output signal frequency range of 5.2khz to 90khz as well. it is recommended to use resistor values with a 1% tolerance. using a potentiometer to trim the ts3002?s output frequency by using a fixed resistor and a potentiometer, the output frequency of the ts3002 can be trimmed as shown in figure 4. by selecting a fixed resistor r1 with a tolerance of 0.1% and a potentiometer p1 with a 5% tolerance, the output frequency can be trimmed to provide a 2% trimming range. as shown in figure 5, r1+p1 and c2 set the output frequency to 25.052khz when p1 = 0 ? and with p1 =200k ? , the resulting output frequency is 24.024khz. using standard resistors to increase fout resolution the ts3002 can be configured to provide a 0.1% resolution on the output frequency as shown in figure 5. to do so, r1 can be set to approximately 10% of the value selected for r2. in addition, r2 and r1 should be chosen with a 0.1% and 1% tolerance, respectively. since r2 is 90% of the total resistance, it has the largest impact on the resolution of the output frequency. with r1 = 91k ? and r2 = 910k ? , the output frequency is 90khz and with r1 = 400k ? and r2 = 4m ? , the output frequency is 23khz. figure 5: setting the ts3002?s output frequency to 0.1% resolution using standard resistors. figure 3: configuring the ts3002 into a voltage- controlled oscillator. figure 4: using a fixed resistor and a potentiometer to trim the ts3002?s output frequency.
ts3002 silicon laboratories, inc. page 12 400 west cesar chavez, austin, tx 78701 ts3002 rev. 1.0 +1 (512) 416-8500 ? www.silabs.com package outline drawing patent notice silicon labs invests in research and development to help our custom ers differentiate in the market with innovative low-power, s mall size, analog-intensive mixed-signal solutions. s ilicon labs' extensive patent portfolio is a testament to our unique approach and wor ld-class engineering team. the information in this document is believed to be accurate in all respects at the time of pub lication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laborat ories assumes no responsibility for the functioning of undescr ibed features or parameters. silicon laboratories reserves the right to make c hanges without further notice. silicon laboratories makes no warra nty, representation or guarantee regarding the suitability of its products for any particu lar purpose, nor does silicon laboratories assume any liability arising out of the application or use of any product or circuit, and specific ally disclaims any and all liability, in cluding without limitation consequential or incidental damages. silicon laboratories products are not designed, int ended, or authorized for use in applica tions intended to support or sustain life, or for any other application in wh ich the failure of the silicon laboratories product could create a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. silicon laboratories and silicon labs are tr ademarks of silicon laboratories inc. other products or brandnames mentioned her ein are trademarks or registered trade marks of their respective holders. bottom view side view 8-pin tdfn22 package outline drawing (n.b., drawing not to scale; all dimensions in mm; jedec mo-229 compliant)
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